MC68030 Datasheet, PDF (340/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Memory Management Unit
(UNABLE TO LOCATE ART)
Figure 9-39. MMU Status Interpretation PTEST Level 0
9.7.5.3 MMU CONFIGURATION EXCEPTION. The exception vector table in the MC68030
assigns a vector for an MMU configuration error exception. The configuration exception
occurs as the result of loading invalid data into the TC, SRP, or CRP register.
When the TC register is loaded with the E bit set, the MMU performs a consistency check
of the values in all the four bit fields. The values in the TIx fields are added until the first zero
is encountered. The values in the PS and IS fields are added to the sum of the TIx fields. If
the sum is not equal to 32, the PMOVE instruction causes an MMU configuration exception.
The instruction also causes a configuration exception when a reserved value ($0-$7) is
placed in the PS field of the TC register.
A PMOVE instruction that loads either the CRP or the SRP causes an MMU configuration
exception if the new value of the DT field is zero (invalid). In this case, the register is loaded
with the new value before the exception is taken.
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MC68030 USER’S MANUAL
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