MC68030 Datasheet, PDF (474/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Instruction Execution Timing
11.6.7 Special-Purpose Move Instruction
The special-purpose MOVE timing table indicates the number of clock periods needed for
the processor to fetch, calculate, and perform the special-purpose MOVE operation on the
control registers or specified effective address. Footnotes indicate when to account for the
appropriate effective address times. The total number of clock cycles is outside the
parentheses. The number of read, prefetch, and write cycles is given inside the parentheses
as (r/p/w). The read, prefetch, and write cycles are included in the total clock cycle number.
All timing data assumes two-clock reads and writes.
Instruction
EXG
Ry,Rx
MOVEC
Cr,Rn
MOVEC
Rn,Cr–A
MOVEC
Rn,Cr–B
MOVE
CCR,Dn
MOVE
CCR,Mem
MOVE
Dn,CCR
MOVE
EA,CCR
MOVE
SR,Dn
MOVE
SR,Mem
#
MOVE
EA,SR
% + MOVEM
EA,RL
% + MOVEM
RL,EA
MOVEP.W
Dn,(d₁₆,An)
MOVEP.W
(d₁₆,An),Dn
MOVEP.L
Dn,(d₁₆,An)
MOVEP.L
(d₁₆,An),Dn
% MOVES
EA,Rn
% MOVE
Rn,EA
MOVE
USP,An
MOVE
An,USP
SWAP
Dn
CA-A
CR-B
n
RL
*
#
%
Control Registers USP, VBR, CAAR, MSP, and ISP
Control Registers SFC, DFC, and CACR
Number of Register to Transfer (n>0)
Register List
Add Calculate Effective Address Time
Add Fetch Effective Address Time
Add Calculate Immediate Address Time
Head
4
6
6
4
2
2
4
0
2
2
0
2
2
4
2
4
2
3
2
4
4
4
Tail
I-Cache Case No-Cache Case
0
4(0/0/0)
4(0/1/0)
0
6(0/0/0)
6(0/1/0)
0
6(0/0/0)
6(0/1/0)
0
12(0/0/0)
12(0/1/0)
0
4(0/0/0)
4(0/1/0)
0
4(0/0/1)
5(0/1/1)
0
4(0/0/0)
4(0/1/0)
0
4(0/0/0)
4(0/1/0)
0
4(0/0/0)
4(0/1/0)
0
4(0/0/1)
5(0/1/1)
0
8(0/0/0)
10(0/2/0)
0
8+4n(n/0/0) 8+4n(n/1/0)
0
4+2n(0/0/n) 4+2n(0/1/n)
0
10(0/0/2)
10(0/1/2)
0
10(2/0/0)
10(2/1/0)
0
14(0/0/4)
14(0/1/4)
0
14(4/0/0)
14(4/1/0)
0
7(1/0/0)
7(1/1/0)
1
5(0/0/1)
6(0/1/1)
0
4(0/0/0)
4(0/1/0)
0
4(0/0/0)
4(0/1/0)
0
4(0/0/0)
4(0/1/0)
+ MOVEM RL,EA – For n Registers (n > 0) and w Wait States
I-Cache Case Timing = w < 2: (8+4n)
w > 2: (8+4n)+(w–2)n
Tail = 0 for all Wait States
MOVEM EA,RL – For n Registers (n > 0) and w Wait States
I-Cache Case Timing = w ≤ 2: (4+2n)+(n–1)w
w > 2: (4+2n)+(n–1)w+(w–2)
Tail =
w ≤ 2: (n–1)w
w > 2: (n)w+(n)(w–2)
MOTOROLA
MC68030 USER’S MANUAL
11-39