MC68030 Datasheet, PDF (329/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Memory Management Unit
9.6 MC68030 AND MC68851 MMU DIFFERENCES
The MC68851 paged memory management unit provides memory management for the
MC68020 as a coprocessor. The on-chip MMU of the MC68030 provides many of the
features of the MC68020/MC68851 combination. The following functions of the MC68851
are not available in the MC68030 MMU:
• Access Levels
• Breakpoint Registers
• Root Pointer Table
• Aliases for Tasks
• Lockable Entries in the ATC
• ATC Entries Defined as Shared Globally
In addition, the following features of the MC68030 MMU differ from the MC68020/MC68851
pair:
• 22-Entry ATC
• Reduced Instruction Set
• Only Control-Alterable Addressing Modes Supported for MMU Instructions
In general, the MC68030 is program compatible with the MC68020/MC68851 combination.
However, in a program for the MC68030, the following instructions must be avoided or
emulated in the exception routine for F-line unimplemented instructions: PVALID,
PFLUSHR, PFLUSHS, PBcc, PDBcc, PScc, PTRAPcc, PSAVE, PRESTORE, and PMOVE
for unsupported registers (CAL, VAL, SCC, BAD, BACx, DRP, and AC). Additionally, the
effective addressing modes supported on the MC68851 that are not emulated by the
MC68030 must be simulated or avoided.
MOTOROLA
MC68030 USER’S MANUAL
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