MC68030 Datasheet, PDF (112/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Processing States
4.1 PRIVILEGE LEVELS
The processor operates at one of two levels of privilege: the user level or the supervisor
level. The supervisor level has higher privileges than the user level. Not all processor or
coprocessor instructions are permitted to execute in the lower privileged user level, but all
are available at the supervisor level. This allows a separation of supervisor and user so the
supervisor can protect system resources from uncontrolled access. The processor uses the
privilege level indicated by the S bit in the status register to select either the user or
supervisor privilege level and either the user stack pointer or a supervisor stack pointer for
stack operations. The processor identifies a bus access (supervisor or user mode) via the
function codes so that differentiation between supervisor and user can be maintained. The
memory management unit uses the indication of privilege level to control and translate
memory accesses to protect supervisor code, data, and resources from access by user
programs.
In many systems, the majority of programs execute at the user level. User programs can
access only their own code and data areas and can be restricted from accessing other
information. The operating system typically executes at the supervisor privilege level. It has
access to all resources, performs the overhead tasks for the user level programs, and
coordinates their activities.
4.1.1 Supervisor Privilege Level
The supervisor level is the higher privilege level. The privilege level is determined by the S
bit of the status register; if the S bit is set, the supervisor privilege level applies, and all
instructions are executable. The bus cycles for instructions executed at the supervisor level
are normally classified as supervisor references, and the values of the function codes on
FC0–FC2 refer to supervisor address spaces.
In a multitasking operating system, it is more efficient to have a supervisor stack space
associated with each user task and a separate stack space for interrupt associated tasks.
The MC68030 provides two supervisor stacks, master and interrupt; the M bit of the status
register selects which of the two is active. When the M bit is set to one, supervisor stack
pointer references (either implicit or by specifying address register A7) access the master
stack pointer (MSP). The operating system sets the MSP for each task to point to a task-
related area of supervisor data space. This separates task-related supervisor activity from
asynchronous, I/O-related supervisor tasks that may be only coincidental to the currently
executing task. The master stack (MSP) can separately maintain task control information for
each currently executing user task, and the software updates the MSP when a task switch
is performed, providing an efficient means for transferring task-related stack items. The
other supervisor stack (ISP) can be used for interrupt control information and workspace
area as interrupt handling routines require.
4-2
MC68030 USER’S MANUAL
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