MC68030 Datasheet, PDF (450/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Instruction Execution Timing
Note that for the head of fiea #<data>.L,D1, 4+op head, the resulting head of 6 is larger than
the instruction-cache-case time of the fetch. A negative number for the execution time of that
portion could result (e.g., 4 –min(6,6) = –2). This result would produce the correct execution
time since the fetch was completely overlapped and the operation was partially overlapped
by the same tail. No changes in the calculation for the operation execution time are required.
Many two-word instructions (e.g., MULU.L, DIV.L, BFSET, etc.) include the fetch immediate
effective address (fiea) time or the calculate immediate effective address (ciea) time in the
execution time calculation. The timing for immediate data of word length (#<data>.W) is
used for these calculations. If the instruction has a source and a destination, the source EA
is used for the table lookup. If the instruction is single operand, the effective address of that
operand is used.
The following example includes multi-word instructions that refer to the fetch immediate
effective address and calculate immediate effective address tables in 11.6 Instruction
Timing Tables.
Instruction
MULU.L
BFCLR
DIVS.L
(D7),D1:D2
$6000{0:8}
#$10000,D3:D4
Head
Tail
CC
1. MULU.L (D7),D1:D2
fiea #<data>.W,Dn
2+op head
0
2
4
0
2
MUL.L EA, Dn
2(op head)
0
44
2. BFCLR $6000{0:8}
fiea #<data>.W,$XXX.W
4
2
6
BFCLR Mem(<5 bytes)
6
0
14
3. DIVS.L #$10000,D3:D4
fiea #<data>.W,#<data>.L 6+op head
0
6
6
0
6
DIVS.L EA,Dn
0(op head)
0
90
MOTOROLA
MC68030 USER’S MANUAL
11-15