MC68030 Datasheet, PDF (533/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Applications Information
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Figure 12-20. Trace or Interrupt Exception
Figure 12-21 illustrates the assertion of the STATUS signal for other exception conditions,
which include MMU address translation cache miss, reset, bus error, address error,
spurious interrupt, autovectored interrupt, and F-line instruction when no coprocessor
responds. Exception processing causes STATUS to assert for three clock cycles to indicate
that normal instruction processing has stopped. Instruction boundaries cannot be
determined in this case since these exceptions are processed immediately, not just at
instruction boundaries.
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Figure 12-21. Other Exceptions
Figure 12-22 shows the assertion of STATUS, indicating that the processor has halted due
to a double bus fault. Once a bus error has occurred, any additional bus error exception
occurring before the execution of the first instruction of the bus error handler routine
constitutes a double bus fault. The processor also halts if it receives a bus error or address
error during the vector table read operations or the prefetch for the first instruction after an
external reset. STATUS remains asserted until the processor is reset.
MOTOROLA
MC68030 USER’S MANUAL
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