MC68030 Datasheet, PDF (245/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Bus Operation
maintains BGACK during the entire bus cycle (or cycles) for which it is bus master. The
following conditions must be met for an external device to assume mastership of the bus
through the normal bus arbitration procedure:
• It must have received BG through the arbitration process.
• AS must be negated, indicating that no bus cycle is in progress, and the external device
must ensure that all appropriate processor signals have been placed in the high-imped-
ance state (by observing specification #7 in MC68030EC/D, MC68030 Electrical Spec-
ifications).
• The termination signal (DSACKx or STERM) for the most recent cycle must have be-
come inactive, indicating that external devices are off the bus (optional, refer to 7.7.3
Bus Grant Acknowledge).
• BGACK must be inactive, indicating that no other bus master has claimed ownership
of the bus.
Figure 7-59 is a flowchart showing the detail involved in bus arbitration for a single device.
Figure 7-60 is a timing diagram for the same operation. This technique allows processing of
bus requests during data transfer cycles.
The timing diagram shows that BR is negated at the time that BGACK is asserted. This type
of operation applies to a system consisting of the processor and one device capable of bus
mastership. In a system having a number of devices capable of bus mastership, the bus
request line from each device can be wire-ORed to the processor. In such a system, more
than one bus request can be asserted simultaneously.
The timing diagram in Figure 7-60 shows that BG is negated a few clock cycles after the
transition of the BGACK signal. However, if bus requests are still pending after the negation
of BG, the processor asserts another BG within a few clock cycles after it was negated. This
additional assertion of BG allows external arbitration circuitry to select the next bus master
before the current bus master has finished with the bus. The following paragraphs provide
additional information about the three steps in the arbitration process.
Bus arbitration requests are recognized during normal processing, RESET assertion, HALT
assertion, and even when the processor has halted due to a double bus fault.
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