MC68030 Datasheet, PDF (367/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Coprocessor Interface Description
during a coprocessor (CPU space) bus cycle, nor does it internally cache data read or
written during coprocessor (CPU space) bus cycles. The MC68030 bus operation is
described in detail in Section 7 Bus Operation.
During coprocessor instruction execution, the MC68030 executes CPU space bus cycles to
access the CIR set. The MC68030 drives the three function code outputs high
(FC2:FC0=111) identifying a CPU space bus cycle. The CIR set is mapped into CPU space
in the same manner that a peripheral interface register set is generally mapped into data
space. The information encoded on the function code lines and address bus of the MC68030
during a coprocessor access is used to generate the chip select signal for the coprocessor
being accessed. Other address lines select a register within the interface set. The
information encoded on the function code and address lines of the MC68030 during a
coprocessor access is illustrated in Figure 10-3.
FUNCTION
CODE
2
0 31
20 19
ADDRESS BUS
16 15 13 12
54
0
1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 CpID 0 0 0 0 0 0 0 0
CIR
CPU SPACE
TYPE FIELD
Figure 10-3. MC68030 CPU Space Address Encodings
Address signals A16-A19 specify the CPU space cycle type for a CPU space bus cycle. The
types of CPU space cycles currently defined for the MC68030 are interrupt acknowledge,
breakpoint acknowledge, and coprocessor access cycles. CPU space type $2
(A19:A16=0010) specifies a coprocessor access cycle.
Signals A13-A15 of the MC68030 address bus specify the coprocessor identification code
CpID for the coprocessor being accessed. This code is transferred from bits 9-11 of the
coprocessor instruction operation word (refer to Figure 10-1) to the address bus during each
coprocessor access. Thus, decoding the MC68030 function code signals and bits A13-A19
of the address bus provides a unique chip select signal for a given coprocessor. The function
code signals and A16-A19 indicate a coprocessor access; A13-A15 indicate which of the
possible seven coprocessors (001-111) is being accessed. Bits A20-A31 and A5-A12 of the
MC68030 address bus are always zero during a coprocessor access.
The MC68010 can emulate coprocessor access cycles in CPU space using the MOVES
instruction.
10.1.4.3 COPROCESSOR INTERFACE REGISTER SELECTION. Figure 10-4 shows that
the value on the MC68030 address bus during a coprocessor access addresses a unique
region of the main processor's CPU address space. Signals A0–A4 of the MC68030 address
bus select the CIR being accessed. The register map for the M68000 coprocessor interface
is shown in Figure 10-5. The individual registers are described in detail in 10.3 Coprocessor
Interface Register Set.
MOTOROLA
MC68030 USER’S MANUAL
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