MC68030 Datasheet, PDF (335/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Memory Management Unit
9.7.3 Transparent Translation Registers
The transparent translation registers (TT0 and TT1) are 32-bit registers that define blocks
of logical address space that are transparently translated. Logical addresses in a
transparently translated block are used as physical addresses, without modification and
without protection checking. The minimum size block that can be defined by either TTx
register is 16 Mbytes of logical address space. The two TTx registers can specify blocks that
overlap. The TTx registers operate independently of the E bit in the TC register and the state
of the MMUDIS signal. A transparent translation register is shown in Figure 9-37.
(UNABLE TO LOCATE ART)
Figure 9-37. Transparent Translation Register (TT0 and TT1) Format
The fields of the transparent translation register are:
Enable (E)
This bit enables transparent translation of the block defined by this register:
0 — Transparent translation disabled
1 — Transparent translation enabled
A reset operation clears this bit.
Cache Inhibit (CI)
This bit inhibits caching for the transparent block:
0 — Caching allowed
1 — Caching inhibited
When this bit is set, the contents of a matching address are not stored in the internal in-
struction or data cache. Additionally, the cache inhibit out signal (CIOUT) is asserted
when this bit is set, and a matching address is accessed, signaling external caches to in-
hibit caching for those accesses.
Read/Write (R/W)
This bit defines the type of access that is transparently translated (for a matching ad-
dress):
0 — Write accesses transparent
1 — Read accesses transparent
Read/Write Mask (RWM)
This bit masks the R/W field:
0 — R/W field used
1 — R/W field ignored
MOTOROLA
MC68030 USER’S MANUAL
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