MC68030 Datasheet, PDF (470/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Instruction Execution Timing
11.6.4 Calculate Immediate Effective Address (ciea) (Continued)
Address Mode
Head
Tail
I-Cache Case No-Cache Case
FULL FORMAT EXTENSION WORD(S) (CONTINUED)
#〈data〉.W,([d₃₂,B],d₃₂)
6
#〈data〉.L,([d₃₂,B],d₃₂)
8
#〈data〉.W,([d₃₂,B],I,d₃₂)
6
#〈data〉.L,([d₃₂,B],I,d₃₂)
8
0
20(1/0/0)
0
22(1/0/0)
0
20(1/0/0)
0
22(1/0/0)
B = Base address; 0, An, PC, Xn, An+Xn, PC+Xn. Form does not affect timing.
I = Index; 0, Xn
% = Total head for address timing includes the head time for the operation.
NOTE: Xn cannot be in B and I at the same time. Scaling and size of Xn do not affect timing
11.6.5 Jump Effective Address
22(1/3/0)
24(1/4/0)
22(1/3/0)
24(1/4/0)
The jump effective address table indicates the number of clock periods needed for the
processor to calculate the specified effective address for the JMP or JSR instructions. Fetch
time is only included for the first level of indirection on memory indirect addressing modes.
The effective addresses are divided by their formats (refer to 2.5 Effective Address
Encoding Summary). For instruction-cache case and for no-cache case, the total number
of clock cycles is outside the parentheses. The number of read, prefetch, and write cycles
is given inside the parentheses as (r/p/w). The read, prefetch, and write cycles are included
in the total clock cycle number.
All timing data assumes two-clock reads and writes.
Address Mode
Head
Tail
I-Cache Case No-Cache Case
SINGLE EFFECTIVE ADDRESS INSTRUCTION FORMAT
% Dn
% An
% (xxx).W
% (xxx).L
2+op head
0
4+op head
0
2+op head
0
2+op head
0
2(0/0/0)
4(0/0/0)
2(0/0/0)
2(0/0/0)
2(0/0/0)
4(0/0/0)
2(0/0/0)
2(0/0/0)
BRIEF FORMAT EXTENSION WORD
(d₈,An,Xn) or (d₈,PC,Xn)
6+op head
0
6(0/0/0)
6(0/0/0)
MOTOROLA
MC68030 USER’S MANUAL
11-35