MC68030 Datasheet, PDF (391/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Coprocessor Interface Description
10.3.4 Restore CIR
The main processor initiates the cpRESTORE instruction by writing a coprocessor format
word to the 16-bit restore register. During the execution of the cpRESTORE instruction, the
coprocessor communicates status and state frame format information to the main processor
through the restore CIR. The offset from the base address of the CIR set for the restore CIR
is $06. Refer to 10.2.3.2 Coprocessor Format Words.
10.3.5 Operation Word CIR
The main processor writes the F-line operation word of the instruction in progress to the 16-
bit operation word CIR in response to a transfer operation word coprocessor response
primitive (refer to 10.4.6 Transfer Operation Word Primitive). The offset from the base
address of the CIR set for the operation word CIR is $08.
10.3.6 Command CIR
The main processor initiates a general category instruction by writing the instruction
command word, which follows the instruction F-line operation word in the instruction stream,
to the 16-bit command CIR. The offset from the base address of the CIR set for the
command CIR is $0A.
10.3.7 Condition CIR
The main processor initiates a conditional category instruction by writing the condition
selector to the 16-bit condition CIR. The offset from the base address of the CIR set for the
condition CIR is $0E. Figure 10-20 shows the format of the condition CIR.
15
(UNDEFINED, RESERVED)
65
0
CONDITION SELECTOR
Figure 10-20. Condition CIR Format
MOTOROLA
MC68030 USER’S MANUAL
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