MC68030 Datasheet, PDF (273/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Exception Processing
EXIT
THESE
INDIVIDUAL
BUS CYCLES
MAY OCCUR
IN ANY ORDER
ONCE PER INSTRUCTION
(CHECK RELATIONSHIP BETWEEN IPEND AND STATUS)
OTHERWISE
IPEND BEFORE STATUS
STAT0 THIS INSTRUCTION BOUNDARY
STAT1 NEXT INSTRUCTION BOUNDARY
WAIT FOR STAT0 OR STAT1*
INDICATE INTERRUPT TO BE PROCESSED
(ASSERT STATUS FOR 2 CLOCKS)
*EXPLAINED FURTHER IN TEXT
NEGATE IPEND
EXECUTE INTERRUPT
ACKNOWLEDGE CYCLE
TEMP SR
S1
T0,T1 0
UPDATE 12-10
-(SP) TEMP
-(SP) PC
-(SP) FORMAT WORD
-(SP) OTHER EXCEPTION-DEPENDENT
INFORMATION
M=0
PC VECTOR TABLE ENTRY
M=1
PREFETCH 3 WORDS
TEMP SR
M0
END OF EXCEPTION PROCESSING
FOR THE INTERRUPT
BEGIN EXECUTION OF THE INTERRUPT
HANDLER ROUTINE OR PROCESS A
HIGHER PRIORITY EXCEPTION
Figure 8-5. Interrupt Exception Processing Flowchart
MOTOROLA
MC68030 USER’S MANUAL
8-19