MC68030 Datasheet, PDF (167/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Bus Operation
15 WORD OPERAND (REGISTER) 0
OP2
OP3
DATA BUS
D31
D16
31
PR
CACHE ENTRY
OP2
OP3
0
N
WORD MEMORY
MSB
LSB
XXX
OP2
OP3
XXX
MC68EC030
SIZ1 SIZ0 A2 A1 A0
1 0001
0 1010
MEMORY CONTROL
DSACK1 DSACK0
L
H
L
H
Figure 7-14. Example of Misaligned Cachable Word Transfer from Word Bus
15
OP0
D31
LONG WORD OPERAND
OP1
OP2
DATA BUS
0
OP3
D0
LONG WORD MEMORY
MC68EC030
MEMORY CONTROL
MSB
UMB
LMB
LSB
SIZ1 SIZ0 A2 A1 A0 DSACK1 DSACK0
XXX
XXX
XXX
OP0
0 0011
L
L
OP1
OP2
OP3
XXX
1 1100
L
L
Figure 7-15. Misaligned Long-Word Transfer to Long-Word Port
Table 7-6 shows that the processor always prefetches instructions by reading a long word
from a long-word address (A1:A0=00), regardless of port size or alignment. When the
required instruction begins at an odd-word boundary, the processor attempts to fetch the
entire 32 bits and loads both words into the instruction cache, if possible, although the
second one is the required word. Even if the instruction access is not cached, the entire 32
bits are latched into an internal cache holding register from which the two instructions words
can subsequently be referenced. Refer to Section 11 Instruction Execution Timing for a
complete description of the cache holding register and pipeline operation.
7-20
MC68030 USER’S MANUAL
MOTOROLA