MC68030 Datasheet, PDF (177/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Bus Operation
Although the synchronous input signals (STERM, CIIN, and CBACK) must be stable for the
appropriate setup and hold times relative to every rising edge of the clock during which AS
is asserted, the assertion or negation of CBACK and CIIN is internally latched on the rising
edge of the clock for which STERM is asserted in a synchronous cycle.
The STERM signal can be generated from the address bus and function code value and
does not need to be qualified with the AS signal. If STERM is asserted and no cycle is in
progress (even if the cycle has begun, ECS is asserted and then the cycle is aborted),
STERM is ignored by the MC68030.
Similarly, CBACK can be asserted independently of the assertion of CBREQ. If a cache
burst is not requested, the assertion of CBACK is ignored.
The assertion of CIIN is ignored when the appropriate cache is not enabled or when cache
inhibit out (CIOUT) is asserted. It is also ignored during write cycles or translation table
searches.
NOTE
STERM and DSACKx should never be asserted during the same
bus cycle.
7.3 DATA TRANSFER CYCLES
The transfer of data between the processor and other devices involves the following signals:
• Address Bus A0–A31
• Data Bus D0–D31
• Control Signals
The address and data buses are both parallel nonmultiplexed buses. The bus master moves
data on the bus by issuing control signals, and the asynchronous/synchronous bus uses a
handshake protocol to insure correct movement of the data. In all bus cycles, the bus master
is responsible for de-skewing all signals it issues at both the start and the end of the cycle.
In addition, the bus master is responsible for de-skewing the acknowledge and data signals
from the slave devices. The following paragraphs define read, write, and read-modify-write
cycle operations. An additional paragraph describes burst mode transfers.
7-30
MC68030 USER’S MANUAL
MOTOROLA