MC68030 Datasheet, PDF (510/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Applications Information
10-MHz
OSCILLATOR
CONTROLLER
CLOCK (40 MHz)
3
BUS CLOCKS
(20 MHz)
MC68EC030
(40 MHz)
FIG 12-8
Figure 12-8. Access Time Computation Diagram
Parameter
Description
a
Address Valid to DSACKx Asserted
b
Address Strobe Asserted to DSACKx Asserted
c
Address Valid to STERM Asserted
d
Address Strobe Asserted to STERM Asserted
e
Address Valid to BERR/HALT Asserted
f
Address Strobe Asserted to BERR/HALT Asserted
g
Address Valid to Data Valid
h
Address Strobe Asserted to Data Valid
System
t_AVDL
t_AVSL
t_SADL
t_SASL
t_AVBHL
t_SABHL
t_AVDV
t_SADV
Equation
12-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
During asynchronous bus cycles, DSACK1 and DSACK0 are used to terminate the current
bus cycle. In true asynchronous operations, such as accesses to peripherals operating at a
different clock frequency, either or both signals may be asserted without regard to the clock,
and then data must be valid a certain amount of time later as defined by specification #31.
With a 16.67-MHz processor, this time is 50 ns after DSACKx asserts; with a 20.0-MHz
processor, this time is 43 ns after DSACK asserts (both numbers vary with the actual clock
frequency).
12-14
MC68030 USER’S MANUAL
MOTOROLA