MC68030 Datasheet, PDF (513/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Applications Information
Memory that is 64 bits wide presents a compromise between the two configurations listed
above.
12.5 STATIC RAM MEMORY BANKS
When the MC68030 is operating at a high clock frequency, a no-wait-state external memory
system will most likely be composed of static RAMs. The following paragraphs discuss three
static memory banks, which may be used as shown or as a starting point for an external
cache design. The designs offer different levels of performance, bus utilization, and cost.
12.5.1 A Two-Clock Synchronous Memory Bank Using SRAMS
The MC68030 normally attains its highest performance when the external memory system
can support a two-clock synchronous bus protocol. This section describes a complete
memory bank containing 64K bytes that can operate with a 20-MHz MC68030 using two-
clock accesses. Also discussed are several options and minor alterations to reduce cost or
power consumption.
Figure 12-9 shows the complete memory bank and its connection to the MC68030. As
drawn, the required parts include:
(8) 16K•4 SRAMs, 35-ns access time with separate I/O pins
(4) 74F244 buffers
(2) 74F32 OR gates
(1) PAL16L8D (or equivalent)
The system must also provide any STERM consolidation circuitry as required (e.g., by the
presence of multiple synchronous memory banks or ports). In Figure 12-9, this consolidation
circuitry is shown as an AND gate.
The memory bank can be divided into three sections:
1. The byte select and address decode section (provided by the PAL),
2. The actual memory section (SRAMs), and
3. The buffer section.
MOTOROLA
MC68030 USER’S MANUAL
12-17