MC68030 Datasheet, PDF (456/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Instruction Execution Timing
Using the general Equation (11-2), calculate as follows:
Execution Time
= CCea₁+[CCop₁-min(Hop₁,Tea₁)]+[CCea₂-min(Hea₂,Top₁)]+
[CCop₂-min(Hop₂,Tea₂)]+[CCea₃-min(Hea₃,Top₂)]+
[CCop₃-min(Hop₃,Tea₃)]+[CCea₄-min(Hea₄,Top₃)]+
[CCop₄-min(Hop₄,Tea₄)]+[CCea₅-min(Hea₅,Top₄)]+
[CCop₅-min(Hop₅,Tea₅)]
= 8+[10-min(4,2)]+[16-min(4,2)]+
[5-min(0,2)]+[4-min(10,3)]+[18-min(6,0)]+[8-min(14,2)]+
[18-min(6,0)]+[14-min(6,0)]+[24-min(2,0)
= 8+8+14+5+1+18;+6+18+14+24
= 116 clock periods
The next example is the data cache hit example from 11.4 Effect of Data Cache with two
wait states per cycle (four-clock read/write). Hits in the data cache and instruction cache are
assumed. Three lines are shown for each timing. The first is the timing from the appropriate
table. The second is the timing adjusted for a data cache hit. The third adds wait states only
to write operations, since the read operations hit in the cache and cause no delay. The third
line for each timing is used to calculate the instruction cache execution time; it is shown in
boldface type.
Instruction
1. ADD.L
2. AND.L
3. MOVE.L
4. TAS
-(A1),D1
D1,([A2])
(A6),(8,A1)
(A3)+
MOTOROLA
MC68030 USER’S MANUAL
11-21