MC68030 Datasheet, PDF (452/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Instruction Execution Timing
NOTE
Data cache hits cannot easily be accounted for in instruction and
operation timings that include an operand fetch in the CCop
(e.g., BFFFO and CHK2). The effect of a data cache hit on such
CCop's has been ignored for computational purposes.
RMC cycles (e.g., TAS and CAS) are forced to miss on data
cache reads. Therefore, a data cache hit has no effect on these
instructions.
The following example assumes data cache hits. The lines that are corrected for data cache
hits are printed in boldface type. These lines are used to calculate the instruction-cache-
case execution time. References are to the preceding rules.
Instruction
1. ADD.L
2. AND.L
3. MOVE.L
4. TAS
-(A1),D1
D1,([A2])
(A6),(8,A1)
(A3)
Head
Tail
CC
1. ADD.L -(A1),D1
Fetch Effective Address
fea -(An)
2
*1c
2
*ADD EA,Dn
0
2. AND.L D1,([A2])
*1a & 2 fea ([B])
4
*AND Dn,EA
0
3. MOVE.L (A6),(8,A1)
fea (An)
1
*1b
1
*MOVE Source, (d_16,An)
2
4.TAS (A3)+
*Cea (An)+
0
*TAS Mem
0
*Corrected for data cache hits.
2-1
4-1(1/0/0)
1
3(1/0/0)
0
2(0/0/1)
0
10(2/0/0)
1
3(0/0/1)
1-1
3–1(1/0/0)
0
2(1/0/0)
0
4(0/0/1)
0
2(0/0/0)
0
12(1/0/1)
NOTE
It is helpful to include the number of operand reads and writes
along with the number of instruction accesses in the CC column
for computing the effect of data cache hits on execution time.
MOTOROLA
MC68030 USER’S MANUAL
11-17