MC68030 Datasheet, PDF (411/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Coprocessor Interface Description
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0
CA PC DR 0
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0
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0
Figure 10-34. Transfer Main Processor Control Register Primitive Format
When the main processor receives this primitive, it reads a control register select code from
the register select CIR. This code determines which main processor control register is
transferred. Table 10-5 lists the valid control register select codes. If the control register
select code is not valid, the MC68030 initiates protocol violation exception processing (refer
to 10.5.2.1 Protocol Violations).
Table 10-5. Main Processor Control Register
Hex
Control Register
x000 Source Function Code (SFC) Register
x001 Destination Function Code (DFC) Register
x002 Cache Control Register (CACR)
x800 User Stack Pointer (USP)
x801 Vector Base Register (VBR)
x802 Cache Address Register (CAAR)
x803 Master Stack Pointer (MSP)
x804 Interrupt Stack Pointer (ISP)
All other codes cause a protocol violation exception
After reading a valid code from the register select CIR, if DR=0, the main processor writes
the long-word operand from the specified control register to the operand CIR. If DR=1, the
main processor reads a long-word operand from the operand CIR and places it in the
specified control register.
MOTOROLA
MC68030 USER’S MANUAL
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