MC68030 Datasheet, PDF (334/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Memory Management Unit
Page Size (PS)
This 4-bit field specifies the system page size:
1000 — 256 bytes
1001 — 512 bytes
1010 — 1K bytes
1011 — 2K bytes
1100 — 4K bytes
1101 — 8K bytes
1110 — 16K bytes
1111 — 32K bytes
All other bit combinations are reserved by Motorola for future use; an attempt to load oth-
er values into this field of the TC register causes an MMU configuration exception.
Initial Shift (IS)
This 4-bit field contains the number of high-order bits of the logical address that are ig-
nored during table search operations. The field contains an integer, 0-15, which sets the
effective size of the logical address to 32-17 bits, respectively. Since all 32 bits of the ad-
dress are compared during address translation, bits ignored due to initial shift cannot have
random values. They must be specified and be consistent with the translation table values
in order to ensure that subsequent address translations match the corresponding entries
in the ATC.
Table Index (TIA, TIB, TIC, and TID)
These 4-bit fields specify the numbers of logical address bits used as the indexes for the
four possible levels of the translation tables (not including the optional level indexed by
the function codes). The index into the highest level table (following the function code,
when used) is specified by TIA, and the lowest level, by TID. The fields contain integers,
0-15. When a zero value in a TIx field is encountered during a table search operation, the
search is over unless the indexed descriptor is a table (indirect) descriptor.
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MC68030 USER’S MANUAL
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