MC68030 Datasheet, PDF (89/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Instruction Set Summary
3.2.8 Program Control Instructions
A set of subroutine call and return instructions and conditional and unconditional branch
instructions perform program control operations. The no operation instruction (NOP) may be
used to force synchronization of the internal pipelines. Table 3–8 summarizes these
instructions.
Table 3-8. Program Control Operations
Instruction
Bcc
DBcc
Scc
BRA
BSR
JMP
JSR
NOP
RTD
RTR
RTS
Operand Syntax Operand Size
Operation
Integer and Floating-Point Conditional
〈label〉
8, 16, 32
if condition true, then PC + d → PC
Dn,〈label〉
16
if condition false, then Dn — 1 → Dn
if Dn ≠ -1, then PC + d → PC
〈ea〉
8
if condition true, then 1's → destination;
else 0's → destination
Unconditional
〈label〉
8, 16, 32
PC + d → PC
〈label〉
8, 16, 32
SP — 4 → SP; PC→(SP); PC + d → PC
〈ea〉
none
destination → PC
〈ea〉
none
SP — 4 → SP; PC→ (SP); destination → PC
none
none
PC + 2 → PC
Returns
#〈d〉
16
(SP) → PC; SP + 4 + d → SP
none
none
(SP) → CCR; SP + 2 → SP; (SP) → PC; SP + 4 → SP
none
none
(SP) → PC; SP + 4→ SP
Letters cc in the integer instruction mnemonics Bcc, DBcc, and Scc specify testing one of the following conditions:
CC — Carry clear
GE — Greater or equal
LS — Lower or same
PL — Plus
CS — Carry set
GT — Greater than
LT — Less than
T
— Always true*
EQ — Equal
HI — Higher
MI — Minus
VC — Overflow clear
F
— Never true*
LE — -Less or equal
NE — Not equal
VS — Overflow set
*Not applicable to the Bcc instructions.
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