MC68030 Datasheet, PDF (463/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Instruction Execution Timing
11.6.2 Fetch Immediate Effective Address (fiea)
The fetch immediate effective address table indicates the number of clock periods needed
for the processor to fetch the immediate source operand and to calculate and fetch the
specified destination operand. In the case of two-word instructions, this table indicates the
number of clock periods needed for the processor to fetch the second word of the instruction
and to calculate and fetch the specified source operand or single operand. The effective
addresses are divided by their formats (refer to 2.5 Effective Address Encoding
Summary). For instruction-cache case and for no-cache case, the total number of clock
cycles is outside the parentheses. The number of read, prefetch, and write cycles is given
inside the parentheses as (r/p/w). The read, prefetch, and write cycles are included in the
total clock cycle number.
All timing data assumes two-clock reads and writes.
Address Mode
Head
Tail
SINGLE EFFECTIVE ADDRESS INSTRUCTION FORMAT
% #〈data〉. W, Dn
% #〈data〉. L, Dn
#〈data〉.W,(An)
#〈data〉.L,(An)
#〈data〉.W,(An)+
#〈data〉.L,(An)+
#〈data〉.W,–(An)
#〈data〉.L,–(An)
#〈data〉.W,(d₁₆,An)
#〈data〉.L,(d₁₆,An)
#〈data〉.W,$XXX.W
#〈data〉.L,$XXX.W
#〈data〉.W,$XXX.L
#〈data〉.L,$XXX.L
# 〈data〉.W, #〈data〉. L
2+op head
0
4+op head
0
1
1
1
0
2
1
4
1
2
2
2
0
2
0
4
0
4
2
6
2
3
0
5
0
6+op head
0
BRIEF FORMAT EXTENSION WORD
#〈data〉.W,(d₈,An,Xn) or (d₈,PC,Xn)
6
2
#〈data〉.L,(d₈,An,Xn) or (d₈,PC,Xn)
8
2
I-Cache Case No-Cache Case
2(0/0/0)
4(0/0/0)
3(1/0/0)
4(1/0/0)
5(1/0/0)
7(1/0/0)
4(1/0/0)
4(1/0/0)
4(1/0/0)
6(1/0/0)
6(1/0/0)
8(1/0/0)
6(1/0/0)
8(1/0/0)
6(0/0/0)
2(0/1/0)
4(0/1/0)
4(1/1/0)
5(1/1/0)
5(1/1/0)
7(1/1/0)
4(1/1/0)
5(1/1/0)
5(1/1/0)
8(1/2/0)
6(1/1/0)
8(1/2/0)
7(1/2/0)
9(1/2/0)
6(0/2/0)
8(1/0/0)
10(1/0/0)
8(1/2/0)
10(1/2/0)
11-28
MC68030 USER’S MANUAL
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