MC68030 Datasheet, PDF (147/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

On-Chip Cache Memories
6.3.1.10 FREEZE INSTRUCTION CACHE. Bit 1, the FI bit, is set to freeze the instruction
cache. When the FI bit is set and a miss occurs in the instruction cache, the entry (or line)
is not replaced. When the FI bit is cleared to zero, a miss in the instruction cache causes the
entry (or line) to be filled. A reset operation clears the FI bit.
6.3.1.11 ENABLE INSTRUCTION CACHE. Bit 0, the EI bit, is set to enable the instruction
cache. When it is cleared, the instruction cache is disabled. A reset operation clears the EI
bit. The supervisor normally enables the instruction cache, but it can clear EI for system
debugging or emulation, as required. Disabling the instruction cache does not flush the
entries. If it is enabled again, the previously valid entries remain valid and may be used.
6.3.2 Cache Address Register
The CAAR is a 32-bit register shown in Figure 6-15. The index field (bits 7-2) contains the
address for the “clear cache entry” operations. The bits of this field correspond to bits 7-2 of
addresses; they specify the index and a long word of a cache line. Although only the index
field is used currently, all 32 bits of the register are implemented and are reserved for use
by Motorola.
31
87
CACHE FUNCTION ADDRESS
INDEX
Figure 6-15. Cache Address Register
21
0
6-18
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