MC68030 Datasheet, PDF (485/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Instruction Execution Timing
11.6.17 Exception-Related Instructions and Operations
The exception-related instruction and operation table indicates the number of clock periods
needed for the processor to perform the specified exception-related action. No additional
tables are needed to calculate total effective execution time for these operations. For
instruction-cache case and for no-cache case, the total number of clock cycles is outside the
parentheses. The number of read, prefetch, and write cycles is given inside the parentheses
as (r/p/w). The read, prefetch, and write cycles are included in the total clock cycle number.
All timing data assumes two-clock reads and writes.
Instruction
BKPT
Interrupt (I-Stack)
Interrupt (M-Stack)
RESET Instruction
STOP
TRACE
TRAP #n
Illegal Instruction
A-Line Trap
F-Line Trap
Privilege Violation
TRAPcc (Trap)
TRAPcc (No Trap)
TRAPcc.W (Trap)
TRAPcc.W (No Trap)
TRAPcc.L (Trap)
TRAPcc.L (No Trap)
TRAPV (Trap)
TRAPV (No Trap)
Head
Tail
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
2
0
4
0
5
0
6
0
6
0
8
0
2
0
4
0
I-Cache Case
9(1/0/0)
23(2/0/4)
33(2/0/8)
518(0/0/0)
8(0/0/0)
22(1/0/5)
18(1/0/4)
18(1/0/4)
18(1/0/4)
18(1/0/4)
18(1/0/4)
22(1/0/5)
4(0/0/0)
24(1/0/5)
6(0/0/0)
26(1/0/5)
8(0/0/0)
22(1/0/5)
4(0/0/0)
No-Cache
Case
9(1/0/0)
24(2/2/4)
34(2/2/8)
518(0/1/0)
8(0/2/0)
24(1/2/5)
20(1/2/4)
20(1/2/4)
20(1/2/4)
20(1/2/4)
20(1/2/4)
24(1/2/5)
4(0/1/0)
26(1/3/5)
6(0/1/0)
28(1/3/5)
8(0/2/0)
24(1/2/5)
4(0/1/0)
11-50
MC68030 USER’S MANUAL
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