MC68030 Datasheet, PDF (438/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Instruction Execution Timing
Prefetch requests are simultaneously submitted to the cache holding register, the instruction
cache, and the bus controller. Thus, even if the instruction cache is disabled, an instruction
prefetch may hit in the cache holding register and cause an external bus cycle to be aborted.
11.2.3 Instruction Cache
The instruction cache services the instruction prefetch portion of the microsequencer. The
prefetch of an instruction that hits in the on-chip instruction cache causes no delay in
instruction execution since no external bus activity is required for the prefetch. The
instruction cache also interacts with the external bus during instruction cache fills following
instruction cache misses.
11.2.4 Data Cache
The data cache services data reads and is updated on data writes. Data operands required
by the execution unit that are accessed from the data cache cause no delay in instruction
execution due to external bus activity for the data fetch. The data cache also interacts with
the external bus during data cache fills following data cache misses.
11.2.5 Bus Controller Resources
Prefetches that miss in the instruction cache cause an external memory cycle to be
performed. Similarly, when data reads miss in the on-chip data cache, an external memory
cycle is required. The time required for either of these bus cycles may be overlapped with
other internal activity.
The bus controller and microsequencer can operate on an instruction concurrently. The bus
controller can perform a read or write while the microsequencer controls an effective
address calculation or sets the condition codes. The microsequencer may also request a
bus cycle that the bus controller cannot perform immediately. In this case, the bus cycle is
queued and the bus controller runs the cycle when the current cycle is complete.
MOTOROLA
MC68030 USER’S MANUAL
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