MC68030 Datasheet, PDF (507/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Applications Information
Table 12-1. Data Bus Activity for Byte, Word, and Long-Word Ports
TransferSi
ze
SIZ1
SIZ0
A1
Byte
0
1
0
0
11
0
0
1
0
1
1
Word
1
0
0
1
0
0
1
0
1
1
0
1
Three Byte 1
1
0
1
1
0
1
1
1
1
1
1
Long Word 0
0
0
0
0
0
0
0
1
0
0
1
Data Bus Active Sections
A0 ^{Byte (B) ;en Word (W) ;en Long-Word (L) Ports}
D31-D24 D23-D16 D15-D8 D7-D0
0
BWL
—
—
—
1
B
WL
—
—
0
BW
—
L
—
1
B
W
—
L
0
BWL
WL
—
—
1
B
WL
L
—
0
BW
W
L
L
1
B
W
—
L
0
BWL
WL
L
—
1
B
WL
L
L
0
BW
W
L
L
1
B
W
—
L
0
BWL
WL
L
L
1
B
WL
L
L
0
BW
W
L
L
1
B
W
—
L
The PAL equations and circuits presented here are not intended to be the optimal
implementation for every system. Depending on the CPU's clock frequency, memory
access times, and system architecture, different circuits may be required.
12.4 MEMORY INTERFACE
The MC68030 is capable of running three types of external bus cycles as determined by the
cycle termination and handshake signals (refer to Section 7 Bus Operation). These three
types of bus cycles are:
1. Asynchronous cycles, terminated by the DSACKx signals, have a minimum duration
of three processor clock periods in which up to four bytes are transferred.
2. Synchronous cycles, terminated by the STERM signal, have a minimum duration of
two processor clock periods in which up to four bytes are transferred.
3. Burst operation cycles, terminated by the STERM and CBACK signals, have a dura-
tion of as little as five processor clock periods in which up to four long words (16 bytes)
are transferred.
12-10
MC68030 USER’S MANUAL
MOTOROLA