MC68030 Datasheet, PDF (526/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Applications Information
For a two-clock bus or burst capability, use of the synchronous bus is mandated, but for a
three or more clock, nonburst cache, the choice of synchronous versus asynchronous
operation must be made. If the bus cycle is terminated only after validation, use of the
synchronous bus is recommended since the address-valid-to-STERM-asserted timing
requirement is longer than the address-valid-to-DSACK-asserted timing for bus cycles of the
same length. If the cache implements late retry, the choice of which bus control mode to use
is less important and depends on system-specific features and control structures. Some
external caches might use both synchronous and asynchronous transfers: synchronous for
hits and asynchronous for misses or vice versa. The following discussion assumes that the
external cache uses the synchronous two-clock protocol, but most statements also apply to
the asynchronous protocol.
If the MC68030 MMU is disabled, all bus cycles use logical addresses. If the MMU is
enabled, the external address bus uses physical addresses (including directly mapped
logical-to-physical addresses from the transparent translation (TTx) registers). These two
modes of operation, logical and physical, affect the maintenance of external caches. For
example, when the external cache uses physical addresses, the cache need not be flushed
on each context switch. Since each task in a system may have its own unique mapping of
the logical address space, a logical cache must be flushed of all entries any time the logical-
to-physical mapping of the system changes (as occurs during a context switch). Since there
is only a single physical address space, this problem does not occur with a physical cache
because all references to a particular operand must utilize the same physical address.
The intended cache size should be evaluated when considering the utility of allowing
multiple tasks to maintain cache entries. If the cache is relatively small and the time between
context switches is large, each task will tend to fill the cache and remove all entries created
during the execution of previous tasks. Conversely, if the cache size is relatively large and
the period between context switches is relatively small, the cache may provide an efficient
sharing of entries.
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MC68030 USER’S MANUAL
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