MC68030 Datasheet, PDF (460/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Instruction Execution Timing
The instruction-cache-case and average no-cache-case columns of the instruction timing
tables contain four sets of numbers, three of which are enclosed in parentheses. The outer
number is the total number of clocks for the given cache case and instruction. The first
number inside the parentheses is the number of operand read cycles performed by the
instruction. The second value inside the parentheses is the maximum number of instruction
bus cycles performed by the instruction, including all prefetches to keep the instruction pipe
filled. Because the second value is the average of the odd-word-aligned case and the even-
word-aligned case (rounded up to an integral number of bus cycles), it is always greater than
or equal to the actual number of bus cycles (one bus cycle per two instruction prefetches).
The third value within the parentheses is the number of write cycles performed by the
instruction. One example from the instruction timing table is:
TOTAL NUMBER OF CLOCKS
NUMBER OF READ CYCLES
MAXIMUM NUMBER OF INSTRUCTION ACCESS CYCLES
NUMBER OF WRITE CYCLES
21 (2 / 3 / 0)
The total numbers of bus-activity clocks and internal clocks (not overlapped by bus activity)
of the instruction in this example are derived as follows:
(2 Reads•2 Clocks/Read)+l(3 Instruction Accesses•2 Clocks/Access)+
(0 Writes•2 Clocks/Write) = 10 Clocks of Bus Activity
21 Total Clocks–10 Bus Activity Clocks = 11 Internal Clocks
The example used here is taken from a no-cache-case ‘fetch effective address' time. The
addressing mode is ([d32,B],I,d32). The same addressing mode under the instruction-
cache-case execution time entry is 18(2/0/0). For the instruction-cache-case execution time,
no instruction accesses are required because the cache is enabled and the sequencer does
not have to access external memory for the instruction words.
The first five timing tables deal exclusively with fetching and calculating effective addresses
and immediate operands. The remaining tables are instruction and operation timings. Some
instructions use addressing modes that are not included in the corresponding instruction
timings. These cases refer to footnotes that indicate the additional table needed for the
timing calculation. All read and write accesses are assumed to take two clock periods.
11.6.1 Fetch Effective Address (fea)
The fetch effective address table indicates the number of clock periods needed for the
processor to calculate and fetch the specified effective address. The effective addresses are
divided by their formats (refer to 2.5 Effective Address Encoding Summary). For
instruction-cache case and for no-cache case, the total number of clock cycles is outside the
parentheses. The number of read, prefetch, and write cycles is given inside the parentheses
as (r/p/w). The read, prefetch, and write cycles are included in the total clock cycle number.
MOTOROLA
MC68030 USER’S MANUAL
11-25