MC68030 Datasheet, PDF (248/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Bus Operation
that the bus is locked. In the case an internal decision to execute another bus cycle, BG is
deferred until the bus cycle has begun.
BG may be routed through a daisy-chained network or through a specific priority-encoded
network. The processor allows any type of external arbitration that follows the protocol.
7.7.3 Bus Grant Acknowledge
Upon receiving BG, the requesting device waits until AS, DSACKx (or synchronous
termination, STERM), and BGACK are negated before asserting its own BGACK. The
negation of the AS indicates that the previous master releases the bus after specification #7
(refer to MC68030EC/D, MC68030 Electrical Specifications). The negation of DSACKx or
STERM indicates that the previous slave has completed its cycle with the previous master.
Note that in some applications, DSACKx might not be used in this way.
General-purpose devices are then connected to be dependent only on AS. When BGACK
is asserted, the device is the bus master until it negates BGACK. BGACK should not be
negated until all bus cycles required by the alternate bus master are completed. Bus
mastership terminates at the negation of BGACK. The BR from the granted device should
be negated after BGACK is asserted. If a BR is still pending after the assertion of BGACK,
another BG is asserted within a few clocks of the negation of BG, as described in the 7.7.4
Bus Arbitration Control. Note that the processor does not perform any external bus cycles
before it reasserts BG in this case.
7.7.4 Bus Arbitration Control
The bus arbitration control unit in the MC68030 is implemented with a finite state machine.
As discussed previously, all asynchronous inputs to the MC68030 are internally
synchronized in a maximum of two cycles of the processor clock.
As shown in Figure 7-61, input signals labeled R and A are internally synchronized versions
of the BR and BGACK signals, respectively. The BG output is labeled G, and the internal
high-impedance control signal is labeled T. If T is true, the address, data, and control buses
are placed in the high-impedance state after the next rising edge following the negation of
AS and RMC. All signals are shown in positive logic (active high), regardless of their true
active voltage level.
7-102
MC68030 USER’S MANUAL
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