MC68030 Datasheet, PDF (200/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Bus Operation
Figure 7-33 is a flowchart of a synchronous write cycle. Figure 7-34 is a functional timing
diagram of this operation with wait states.
CONTROLLER
ADDRESS DEVICE
1) ASSERT ECS/OCS FOR ONE-HALF CLOCK
2) DRIVE ADDRESS ON A31–A0
3) DRIVE FUNCTION ON FC2–FC0
4) DRIVE SIZE (SIZ1–SIZ0) (FOUR BYTES)
5) SET R/W TO WRITE
6) CACHE INHIBIT OUT (CIOUT) BECOMES VALID
7) ASSERT ADDRESS STROBE (AS)
8) ASSERT DATA BUFFER ENABLE (DBEN)
ASSERT DATA BUFFER ENABLE (DBEN)
9) DRIVE DATA LINES D31–D0
10) ASSERT DATA STROBE (DS) IF WAIT STATES)
TERMINATE OUTPUT TRANSFER
1) NEGATE AS AND DS
2) REMOVE DATA FROM D31-0
3) NEGATE DBEN
EXTERNAL DEVICE
ACCEPT DATA
1) DECODE ADDRESS
2) STORE DATA ON D31-D0
3) ASSERT SYNCHRONOUS TERMINATION (STERM)
TERMINATE CYCLE
START NEXT CYCLE
1) NEGATE STERM
Figure 7-33. Synchronous Write Cycle Flowchart
State 0
The write cycle starts with S0. The processor drives ECS low, indicating the beginning of
an external cycle. When the cycle is the first cycle of a write operation, OCS is driven low
at the same time. During S0, the processor places a valid address on A0–A31 and valid
function codes on FC0–FC2. The function codes select the address space for the cycle.
The processor drives R/W low for a write cycle. SIZ0–SIZ1 become valid, indicating the
number of bytes to be transferred. CIOUT also becomes valid, indicating the state of the
MMU CI bit in the address translation descriptor or in the appropriate TTx register.
State 1
One-half clock later in S1, the processor asserts AS, indicating that the address on the
address bus is valid. The processor also asserts DBEN during S1, which may be used to
enable the external data buffers. In addition, the ECS (and OCS, if asserted) signal is
negated during S1.
7-54
MC68030 USER’S MANUAL
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