MC68030 Datasheet, PDF (272/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Exception Processing
CLK
IPL2-IPL0
IPEND
IPLs RECOGNIZED
ASSERT IPEND
IPLs SYNCHRONIZED
COMPARE REQUEST
WITH MASK IN SR
Figure 8-4. Assertion of IPEND
The state of the IPEND signal is internally checked by the processor once per instruction,
independently of bus operation. In addition, it is checked during the second instruction
prefetch associated with exception processing. Figure 8-5 is a flowchart of the interrupt
recognition and associated exception processing sequence.
To predict the instruction boundary during which a pending interrupt is processed, the timing
relationship between the assertion of IPEND for that interrupt and the assertion of STATUS
must be examined. Figure 8-6 shows two examples of interrupt recognition. The first
assertion of STATUS after IPEND is denoted as STAT0. The next assertion of STATUS is
denoted as STAT1. If STAT0 begins on the falling edge of the clock immediately following
the clock edge that caused IPEND to assert (as shown in example 1), STAT1 is at least two
clocks long, and, when there are no other pending exceptions, the interrupt is acknowledged
at the boundary defined by STAT1. If IPEND is asserted with more setup time to STAT0, the
interrupt may be acknowledged at the boundary defined by STAT0 (as shown in example
2). In that case, STAT0 is asserted for two clocks, signaling this condition.
If no higher priority interrupt has been synchronized, the IPEND signal is negated during
state 0 (S0) of an interrupt acknowledge cycle (refer to 7.4.1.1 Interrupt Acknowledge
Cycle — Terminated Normally), and the IPLx signals for the interrupt being acknowledged
can be negated at this time.
8-18
MC68030 USER’S MANUAL
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