MC68030 Datasheet, PDF (458/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Instruction Execution Timing
Using the general Equation (11-2), calculate as follows:
Execution Time
= CCea₁+[CCop₁-min(Hea₁,Top₁)]+[CCea₂-min(Hea₂,Top₁)]+
[CCop₂-min(Hop₂,Tea₂)]+[CCea₃-min(Hea₃,Top₂)]+
[CCop₃-min(Hop₃,Tea₃)]+[CCea₄-min(Hea₄,Top₃)]+
[CCop₄-min(Hop₄,Tea₄)]
= 3+[2-min(0,1)]m+[12-min(4,0)]+
[5-min(0,0)]+[2-min(1,3)]+
[6-min(2,0)]+[2-min(0,2)]+
[14-min(3,0)
= 3+2+12+5+1+6+2+14
= 45 clock periods
A similar analysis can be constructed for the average no-cache case. Since the average no-
cache-case time assumes two clock periods per bus cycle (i.e., no wait states), the timing
given in the tables does not apply directly to systems with wait states. To approximate the
average no-cache-case time for an instruction or effective address with W wait states, use
the following formula:
NCC = NCC_t+(# of data reads and writes)•W+
(max. # of instruction accesses)•W
where:
NCC_t is the no-cache-case timing value from the appropriate table.
The number of data reads, data writes, and maximum instruction accesses are found in
the appropriate table.
The average no-cache-case timing obtained from this formula is equal to or greater than the
actual no-cache-case timing since the number of instruction accesses used is a maximum
(the values in the tables are always rounded up) and no overlap is assumed.
MOTOROLA
MC68030 USER’S MANUAL
11-23