MC68030 Datasheet, PDF (262/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Exception Processing
The processor begins exception processing for a bus error by making an internal copy of the
current status register. The processor then enters the supervisor privilege level (by setting
the S bit in the status register) and clears the trace bits. The processor generates exception
vector number 2 for the bus error vector. It saves the vector offset, program counter, and the
internal copy of the status register on the stack. The saved program counter value is the
logical address of the instruction that was executing at the time the fault was detected. This
is not necessarily the instruction that initiated the bus cycle, since the processor overlaps
execution of instructions. The processor also saves the contents of some of its internal
registers. The information saved on the stack is sufficient to identify the cause of the bus
fault and recover from the error.
For efficiency, the MC68030 uses two different bus error stack frame formats. When the bus
error exception is taken at an instruction boundary, less information is required to recover
from the error, and the processor builds the short bus fault stack frame as shown in Table
8-7. When the exception is taken during the execution of an instruction, the processor must
save its entire state for recovery and uses the long bus fault stack frame shown in Table 8-
7. The format code in the stack frame distinguishes the two stack frame formats. Stack
frame formats are described in detail in 8.4 Exception Stack Frame Formats.
If a bus error occurs during the exception processing for a bus error, address error, or reset
or while the processor is loading internal state information from the stack during the
execution of an RTE instruction, a double bus fault occurs, and the processor enters the
halted state as indicated by the continuous assertion of the STATUS signal. In this case, the
processor does not attempt to alter the current state of memory. Only an external RESET
can restart a processor halted by a double bus fault.
8.1.3 Address Error Exception
An address error exception occurs when the processor attempts to prefetch an instruction
from an odd address. This exception is similar to a bus error exception, but is internally
initiated. A bus cycle is not executed, and the processor begins exception processing
immediately. After exception processing commences, the sequence is the same as that for
bus error exceptions described in the preceding paragraphs, except that the vector number
is 3 and the vector offset in the stack frame refers to the address error vector. Either a short
or long bus fault stack frame may be generated. If an address error occurs during the
exception processing for a bus error, address error, or reset, a double bus fault occurs.
8-8
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