MC68030 Datasheet, PDF (388/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Coprocessor Interface Description
10.2.3.4.2 Protocol. Figure 10-18 shows the protocol for the coprocessor context restore
instruction. When the main processor executes a cpRESTORE instruction, it first reads the
coprocessor format word from the effective address in the instruction. This format word
contains a format code and a length field. During cpRESTORE operation, the main
processor retains a copy of the length field to determine the number of bytes to be
transferred to the coprocessor during the cpRESTORE operation and writes the format word
to the restore CIR to initiate the coprocessor context restore.
(UNABLE TO LOCATE ART)
Figure 10-18. Coprocessor Context Restore Instruction Protocol
When the coprocessor receives the format word in the restore CIR, it must terminate any
current operations and evaluate the format word. If the format word represents a valid
coprocessor context as determined by the coprocessor design, the coprocessor returns the
format word to the main processor through the restore CIR and prepares to receive the
number of bytes specified in the format word through its operand CIR.
After writing the format word to the restore CIR the main processor continues the
cpRESTORE dialog by reading that same register. If the coprocessor returns a valid format
word, the main processor transfers the number of bytes specified by the format word at the
effective address to the operand CIR.
If the format word written to the restore CIR does not represent a valid coprocessor state
frame, the coprocessor places an invalid format word in the restore CIR and terminates any
current operations. The main processor receives the invalid format code, writes an abort
mask (refer to 10.2.3.2.3 Invalid Format Word) to the control CIR, and initiates format error
exception processing (refer to 10.5.1.5 Format Errors).
The cpRESTORE instruction is a privileged instruction. When the main processor accesses
a cpRESTORE instruction, it checks the supervisor bit in the status register. If the MC68030
attempts to execute a cpRESTORE instruction while at the user privilege level (status
register bit [13]=0), it initiates privilege violation exception processing without accessing any
of the coprocessor interface registers (refer to 10.5.2.3 Privilege Violations).
10.3 COPROCESSOR INTERFACE REGISTER SET
The instructions of the M68000 coprocessor interface use registers of the CIR set to
communicate with the coprocessor. These CIRs are not directly related to the coprocessor's
programming model.
Figure 10-4 is a memory map of the CIR set. The registers denoted by asterisks (*) must be
included in a coprocessor interface that implements coprocessor instructions in all four
categories. The complete register model must be implemented if the system uses all of the
coprocessor response primitives defined for the M68000 coprocessor interface.
The following paragraphs contain detailed descriptions of the registers.
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MC68030 USER’S MANUAL
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