MC68030 Datasheet, PDF (169/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Bus Operation
31
OP0
D31
LONG WORD OPERAND (REGISTER)
OP1
OP2
0
OP3
31
PR2
31
OP1
CACHE ENTRIES
PR1
PR
OP2
OP3
DATA BUS
D0
0
OP0
0
N
LONG WORD MEMORY
MSB
UMB
LMB
PR2
PR1
PR
MC68EC030
MEMORY CONTROL
LSB
SIZ1 SIZ0 A2 A1 A0 DSACK1 DSACK0
OP0
0 0011
L
L
OP1
OP2
OP3
N
1 1100
L
L
Figure 7-17. Misaligned Cachable Long-Word Transfer from Long-Word Bus
7.2.4 Address, Size, and Data Bus Relationships
The data transfer examples show how the MC68030 drives data onto or receives data from
the correct byte sections of the data bus. Table 7-7 shows the combinations of the size
signals and address signals that are used to generate byte enable signals for each of the
four sections of the data bus for noncachable read cycles and all write cycles if the
addressed device requires them. The port size also affects the generation of these enable
signals as shown in the table. The four columns on the right correspond to the four byte
enable signals. Letters B, W, and L refer to port sizes: B for 8-bit ports, W for 16-bit ports,
and L for 32-bit ports. The letters B, W, and L imply that the byte enable signal should be
true for that port size. A dash (—) implies that the byte enable signal does not apply.
The MC68030 always drives all sections of the data bus because, at the start of a write
cycle, the bus controller does not know the port size. The byte enable signals in the table
apply only to read operations that are not to be internally cached and to write operations.
For cachable read cycles, during which the data is cached, the addressed port must drive
all sections of the bus on which it resides.
7-22
MC68030 USER’S MANUAL
MOTOROLA