MC68030 Datasheet, PDF (258/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Exception Processing
The MC68030 provides the STATUS signal to identify instruction boundaries and some
exceptions. As shown in Table 8-2, STATUS indicates an instruction boundary and
exceptions to be processed, depending on the state of the internal microsequencer. In
addition, STATUS indicates when an MMU address translation cache miss has occurred
and the processor is about to begin a table search access for the logical address that caused
the miss. Instruction-related exceptions do not cause the assertion of STATUS as shown in
Table 8-1. For STATUS signal timing information, refer to Section 12 Applications
Information.
Table 8-2. Microsequencer STATUS Indications
Asserted for
1 Clock
2 Clocks
3 Clocks
Continuously
Indicates
Sequencer at instruction boundary will begin execution of next instruction.
Sequencer at instruction boundary but will not begin the next instruction
immediately due to:
• pending trace exception
OR
• pending interrupt exception
MMU address translation cache miss — processor to begin table serach
OR
Exception processing to begin for:
• reset OR
• bus error OR
• address error OR
• spurious interrupt OR
• autovectored interrupt OR
• F-line instruction (no coprocessor responded)
Processor halted due to double bus fault.
8-4
MC68030 USER’S MANUAL
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