MC68030 Datasheet, PDF (518/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Applications Information
Not all systems require the performance of 20-MHz two-clock bus cycles, nor will all systems
be able to afford the fast devices. Fortunately, several small changes to this design could
assist designers with different cost/performance ratios. The simplest and most direct
method is to reduce the clock frequency of the MC68030. For instance, if the clock
frequency is below approximately 18.1 MHz, the same control logic supports two-clock bus
cycles with 45-ns memory (55 ns if < 15.8 MHz). If 20 MHz is still the frequency of choice,
the designer may choose to run three-clock bus cycles. This can be accomplished with the
addition of a flip-flop to delay the TERM signal by one clock. The resulting memory access
time is over 85 ns with a 20-MHz processor running with three-clock bus cycles.
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MC68030 USER’S MANUAL
MOTOROLA