MC68030 Datasheet, PDF (290/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Memory Management Unit
• 0-15 Upper Logical Address Bits Can Be Ignored (Using Initial Shift)
• Portions of Tables Can Be Undefined (Using Limits)
• Write Protection and Supervisor Protection
• History Bits Automatically Maintained in Page Descriptors
• Cache Inhibit Output (CIOUT) Signal Asserted on Page Basis
• External Translation Disable Input Signal (MMUDIS)
• Subset of Instruction Set Defined by MC68851
The MMU completely overlaps address translation time with other processing activity when
the translation is resident in the ATC. ATC accesses operate in parallel with the on-chip
instruction and data caches.
Figure 9-1 is a block diagram of the MC68030 showing the relationship of the MMU to the
execution unit and the bus controller. For an instruction or operand access, the MC68030
simultaneously searches the caches and searches for a physical address in the ATC. If the
translation is available, the MMU provides the physical address to the bus controller and
allows the bus cycle to continue. When the instruction or operand is in either of the on-chip
caches on a read cycle, the bus controller aborts the bus cycle before address strobe is
asserted. Similarly, the MMU causes a bus cycle to abort before the assertion of address
strobe when a valid translation is not available in the ATC or when an invalid access is
attempted.
An MMU disable input signal (MMUDIS) is provided that dynamically disables address
translation for emulation, diagnostic, or other purposes.
The programming model of the MMU (see Figure 9-2) consists of two root pointer registers,
a control register, two transparent translation registers, and a status register. These
registers can only be accessed by supervisor programs. The CPU root pointer register
points to an address translation tree structure in memory that describes the logical-to-
physical mapping for user accesses or for both user and supervisor accesses. The
supervisor root pointer register optionally points to an address translation tree structure for
supervisor mappings. The translation control register is comprised of fields that control the
translation operation. Each transparent translation register can define a block of logical
addresses that are used as physical addresses (without translation). The MMU status
register contains accumulated status information from a translation performed as a part of a
PTEST instruction.
9-2
MC68030 USER’S MANUAL
MOTOROLA