MC68030 Datasheet, PDF (373/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Coprocessor Interface Description
Figure 10-8 shows the protocol for a conditional category coprocessor instruction. The main
processor initiates execution of an instruction in this category by writing a condition selector
to the condition CIR. The coprocessor decodes the condition selector to determine the
condition to evaluate. The coprocessor can use response primitives to request that the main
processor provide services required for the condition evaluation. After evaluating the
condition, the coprocessor returns a true/false indicator to the main processor by placing a
null primitive (refer to 10.4.4 Null Primitive) in the response CIR. The main processor
completes the coprocessor instruction execution when it receives the condition indicator
from the coprocessor.
(UNABLE TO LOCATE ART)
Figure 10-8. Coprocessor Interface Protocol for Conditional
Category Instructions
10.2.2.1 BRANCH ON COPROCESSOR CONDITION INSTRUCTION. The conditional
instruction category includes two formats of the M68000 Family branch instruction. These
instructions branch on conditions related to the coprocessor operation. They execute
similarly to the conditional branch instructions provided in the M68000 Family instruction set.
10.2.2.1.1 Format. Figure 10-9 shows the format of the branch on coprocessor condition
instruction that provides a word-length displacement. Figure 10-10. shows the format of the
instruction that includes a long-word displacement.
15
14
13
12
11
9
8
7
6
5
0
1
1
1
1
CpID
0
1
0
CONDITION SELECTOR
OPTIONAL COPROCESSOR-DEFINED WORDS
DISPLACEMENT
Figure 10-9. Branch on Coprocessor Condition Instruction (cpBcc.W)
15
14
13
12
11
9
8
7
6
5
0
1
1
1
1
CpID
0
1
1
CONDITION SELECTOR
OPTIONAL COPROCESSOR-DEFINED WORDS
DISPLACEMENT-HIGH
DISPLACEMENT-LOW
Figure 10-10. Branch On Coprocessor Condition Instruction (cpBcc.L)
The first word of the branch on coprocessor condition instruction is the F-line operation
word. Bits [15:12]=1111 and bits [11:9] contain the identification code of the coprocessor
that is to evaluate the condition. The value in bits [8:6] identifies either the word or the long-
word displacement format of the branch instruction, which is specified by the cpBcc.W or
cpBcc.L mnemonic, respectively.
MOTOROLA
MC68030 USER’S MANUAL
10-13