MC68030 Datasheet, PDF (496/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Instruction Execution Timing
11.8 INTERRUPT LATENCY
In real-time systems, the response time required for a processor to service an interrupt is a
very important factor pertaining to overall system performance. Processors in the M68000
Family support asynchronous assertion of interrupts and begin processing them on
subsequent instruction boundaries. The average interrupt latency is quite short, but the
maximum latency is often critical because real-time interrupts cannot require servicing in
less than the maximum interrupt latency. The maximum interrupt latency for the MC68030
alone is approximately 200 clock cycles (for the MOVEM.L ([d₃₂,An],Xn,d₃₂), D0-D7/A0-A7
instruction where the last data fetch is aborted with a bus error), but when the MMU is
enabled, some operations can take several times longer to execute.
Interrupt latency in systems using the MMU is affected by the length of the main processor
instructions, the address translation tree configuration, the number of translation tree
searches required by the instructions, the access time of main memory, and the width of the
data bus connecting the MC68030 to main memory. It is important to note that the address
translation tree configuration is under software control and can strongly affect the system
interrupt latency. The maximum interrupt latency for a given system configuration can be
computed by adding the length of the longest main processor instruction to the time required
for the maximum number of translation tree searches that the instruction could require. For
the MC68030 microprocessor, one instruction of particular interest is a memory-to-memory
move with memory indirect addressing for both the source and destination, with all of the
code and data items crossing page boundaries. The assembler syntax for this instruction is:
MOVE.L (od,[bd,An,Rm]),(od,[bd,An,Rm])
This instruction can cause ten address translation tree searches: two for the instruction
stream, two for the source indirect address, two for the destination indirect address, two for
the operand fetch, and two for the destination write. System software can reduce the
maximum number of translation searches by placing additional restrictions on generated
code. For example, if the language translators in the system only generate long words
aligned on long-word boundaries, the indirect address and operands can cause only one
translation search each. This reduces the number of searches for the instruction to a
maximum of six.
MOTOROLA
MC68030 USER’S MANUAL
11-61