MC68030 Datasheet, PDF (442/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Instruction Execution Timing
11.3.2 Overlap and Best Case
Overlap is the time, measured in clock periods, that an instruction executes concurrently
with the previous instruction. In Figure 11-2, a portion of instructions A and B execute
simultaneously. The overlap time decreases the overall execution time for the two
instructions. Similarly, an overlap period between instructions B and C reduces the overall
execution time of these two instructions.
INSTRUCTION A
INSTRUCTION B
INSTRUCTION C
OVERLAP
OVERLAP
Figure 11-2. Simultaneous Instruction Execution
Each instruction contributes to the total overlap time. As shown in Figure 11-2, a portion of
time at the beginning of the execution of instruction B can overlap the end of the execution
time of instruction A. This time period is called the head of instruction B. The portion of time
at the end of instruction A that can overlap the beginning of instruction B is called the tail of
instruction A. The total overlap time between instructions A and B consists of the lesser of
the tail of instruction A or the head of instruction B. Refer to the instruction timing tables in
11.6 Instruction Timing Tables for head and tail times.
Figure 11-3 shows the timing relationship of the factors that comprise the instruction-cache
case time for either an effective address calculation (CCea) or for an operation (CCop). In
Figure 11-12, the best case execution time for instruction B occurs when the instruction-
cache-case times for instruction B and instruction A overlap so that the head of instruction
B is completely overlapped with the tail of instruction A.
MOTOROLA
MC68030 USER’S MANUAL
11-7