MC68030 Datasheet, PDF (204/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Bus Operation
S0 S1 S2 S3 Si
CLK
Si S4 S5 S6 S7
A31-A0
FC2-FC0
SIZ1
SIZ0
R/W
RMC
ECS
OCS
AS
DS
DSACK1
DSACK0
STERM
CIIN
CIOUT
CBREQ
CBACK
D31-D0
DBEN
Figure 7-36. Synchronous Read-Modify-Write Cycle Timing — CIIN Asserted
State 0
The processor asserts ECS and OCS in S0 to indicate the beginning of an external
operand cycle. The processor also asserts RMC in S0 to identify a read-modify-write
cycle. The processor places a valid address on A0–A31 and valid function codes on FC0–
FC2. The function codes select the address space for the operation. SIZ0–SIZ1 become
valid in S0 to indicate the operand size. The processor drives R/W high for a read cycle
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MC68030 USER’S MANUAL
MOTOROLA