MC68030 Datasheet, PDF (532/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Applications Information
from the new address translation base. The Test Condition, Decrement, and Branch (DBcc)
instruction causes two refill requests when the condition being tested is false. To optimize
branching performance, the DBcc instruction requests a refill before the condition is tested.
If the condition is false, another refill is requested to continue with the next sequential
instruction.
Figure 12-19 illustrates the relation between the CLK signal and normal instruction
boundaries as identified by the STATUS signal. STATUS asserting for one clock cycle
identifies normal instruction boundaries. Note that the assertion of REFILL does not
necessarily correspond to the assertion of STATUS. Both STATUS and REFILL assert and
negate from the falling edge of the CLK signal.
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Figure 12-19. Normal Instruction Boundaries
Figure 12-20 shows a normal instruction boundary followed by a trace or interrupt exception
boundary. STATUS asserting for two clock cycles identifies a trace or interrupt exception.
Instruction boundary information is still present since both trace and interrupt exceptions are
processed only at instruction boundaries. Before the exception handler instructions are
prefetched, the REFILL signal asserts (not shown) to identify a change in program flow.
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MC68030 USER’S MANUAL
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