MC68030 Datasheet, PDF (560/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Index
Indirect Descriptor 9-27
Invalid Descriptor 9-26
Page Descriptor 9-25
Table Descriptor 9-24
Side Effects, MMU Register 9-61
Signal
Address Strobe 5-5, 7-3–7-4, 7-26
AS 5-5, 7-3–7-4, 7-26
Autovector 5-8, 7-6, 7-29, 7-71
AVEC 5-8, 7-6, 7-29, 7-71
BERR 5-9, 6-19, 7-6, 7-27, 8-7, 8-22,
8-25
BG 5-9, 7-43, 7-96
BGACK 5-9, 7-97
BR 5-8, 7-43, 7-60, 7-96
Bus Error 5-9, 6-11, 7-6, 7-27, 8-7, 8-22,
8-25
Bus Grant 5-9, 7-43, 7-96
Bus Grant Acknowledge 5-9, 7-97
Bus Request 5-8, 7-43, 7-60, 7-96
Cache Burst Acknowledge 5-7, 6-16,
7-24, 7-30
Cache Burst Request 5-7, 6-16, 7-6,
7-30, 7-48
Cache Disable 5-10, 6-3
Cache Inhibit Input 5-7, 6-3, 6-9, 7-3,
7-30
Cache Inhibit Output 5-7, 6-3, 6-9, 7-30,
9-2, 9-13
CBACK 5-7, 6-16, 7-3, 7-24, 7-30
CBREQ 5-7, 6-16, 7-6, 7-30, 7-48
CDIS 5-10, 6-3
CIIN 5-7, 6-3, 6-9, 6-15, 7-3, 7-26
CIOUT 5-7, 6-3, 6-9, 7-30, 9-2, 9-17
CLK 5-11, 7-54
Clock 5-11, 7-54
Data Buffer Enable 5-6, 7-5, 7-51
Data Strobe 5-6, 7-5, 7-27
DBEN 5-6, 7-5, 7-31
DS 5-6, 7-5, 7-27
DSACK0 5-6, 6-11, 6-14, 7-5–7-6, 7-26
DSACK1 5-6, 6-11, 6-14, 7-5–7-6, 7-26
ECS 5-5, 7-3, 7-26
External Cycle Start 5-5, 7-3, 7-26
HALT 5-9, 7-6, 7-27
Halt 5-9, 7-6, 7-27
Internal Microsequencer Status 5-10,
7-94, 8-4, 8-18, 8-25
Interrupt Pending 5-8, 8-17–8-18
IPEND 5-8, 8-17–8-18
MMU Disable 5-10, 9-2, 9-15
MMUDIS 5-10, 9-2, 9-15
OCS 5-5, 7-3, 7-31
Operand Cycle Start 5-5, 7-3, 7-31
Pipeline Refill 5-10, 6-5
Read-Modify-Write 5-5, 7-4, 7-43
Read/Write 5-5, 7-4, 7-36
REFILL 5-10, 6-5
RESET 5-9, 7-97, 9-15, 9-61, 12-40
Reset 5-9, 7-97, 9-15, 9-61, 12-40
RMC 5-5, 7-4, 7-43, 12-4
R/W 5-5, 7-4, 7-36
SIZ0 5-4, 7-4, 7-8–7-9, 7-13, 7-22
SIZ1 5-4, 7-4, 7-8–7-9, 7-13, 7-22
STATUS 5-10, 7-94, 8-4, 8-7–8-8
STERM 5-6, 6-14, 6-16, 7-3, 7-6, 7-26
Signal Assertion Results, Asynchronous
Cycle 7-78
Signal Groups 5-1
Signal Index 5-2
Signal Routing, Adapter Board 12-2
Signal Summary 5-11
Signals
A0-A1 7-8, 7-22
A0-A31 5-4, 7-4, 7-31
Bus Control 7-3
Bus Transfer 7-1
Data Bus Write Enable 7-22
Data Transfer and Size Acknowledge
5-6, 6-11, 6-14, 7-5–7-6, 7-26
D0-D31 5-4, 7-5, 7-30
FC0-FC2 5-4, 6-6, 7-4, 7-31
Function Code 5-4, 6-6, 7-4, 7-31
Instruction Boundary 12-37
Interrupt Exception 12-38
Interrupt Priority Level 5-8, 7-69, 8-13
IPL0-IPL2 5-8, 7-69, 8-13
MC68851 12-4
Other Exception 12-38
Processor Halted 12-39
Trace Exception 12-38
Transfer Size 5-4, 7-4, 7-8–7-9, 7-22
Single Entry Cache Filling 6-10
Single Operand Instruction Timing Table
11-44
Size Restrictions, Table Index 9-10
Index-12
MC68030 USER’S MANUAL
MOTOROLA