MC68030 Datasheet, PDF (330/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Memory Management Unit
9.7 REGISTERS
The registers of the MMU described here are part of the supervisor programming model for
the MC68030.
The six registers that control and provide status information for address translation in the
MC68030 are the CPU root pointer register (CRP), the supervisor root pointer register
(SRP), the translation control register (TC), two independent transparent translation control
registers (TT0 and TT1), and the MMU status register (MMUSR). These registers can be
accessed directly by programs that execute only at the supervisor level.
9.7.1 Root Pointer Registers
The supervisor root pointer (SRP), used for supervisor accesses only, is enabled or disabled
in software. The CPU root pointer (CRP) corresponds to the current translation table for user
space (when the SRP is enabled) or for both user and supervisor space (when the SRP is
disabled). The CRP is a 64-bit[lz register that contains the address and related status
information of the root of the translation table tree for the current task. When a new task
begins execution, the operating system typically writes a new root pointer descriptor to the
CRP. A new translation table address implies that the contents of the address translation
cache (ATC) may no longer be valid. Therefore, the instruction that loads the CRP can
optionally flush the ATC.
The SRP is a 64-bit register that optionally contains the address and related status
information of the root of the translation table for supervisor area accesses. The SRP is used
when operating at the supervisor privilege level only when the supervisor root pointer enable
bit (SRE) of the translation control register (TC) is set. The instruction that loads the SRP
can optionally flush the ATC. The format of the CRP and SRP is shown in Figure 9-35 and
defines the following fields:
Lower/Upper (L/U)
Specifies that the value contained in the limit field is to be used as the unsigned lower
limit of indexes into the translation tables when this bit is set. When this bit is cleared,
the limit field is the unsigned upper limit of the translation table indexes.
9-42
MC68030 USER’S MANUAL
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