MC68030 Datasheet, PDF (216/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Bus Operation
State 7
During this state, the processor negates CBREQ, and the memory device may negate
CBACK. Aside from this, all other bus signals driven by the processor remain driven.
The same hold times for STERM and data described for S3 apply here.
State 8
This state is identical to S4 except that CBREQ is negated, indicating that the processor
cannot continue to accept more data after this. The data latched at the end of S8
corresponds to the fourth long word of the burst.
State 9
The processor negates AS, DS, and DBEN during S9. It holds the address, R/W, SIZ0–
SIZ1, and FC0–FC2 valid throughout S9. The same hold times for data described for S3
apply here.
Note that the address bus of the MC68030 remains driven to a constant value for the
duration of a burst transfer operation (including the first transfer before burst mode is
entered). If an external memory system requires incrementing of the long-word base
address to supply successive long words of information, this function must be performed by
external hardware. Additionally, in the case of burst transfers that cross a 16-byte boundary
(i.e., the first long word transferred is not located at A3/A2=00), the external hardware must
correctly control the continuation or termination of the burst transfer as desired. The burst
may be terminated by negating CBACK during the transfer of the most significant long word
of the 16-byte image (A3/A2=11) or may be continued (with CBACK asserted) by providing
the long word located at A3/A2=00 (i.e., the count sequence wraps back to zero and
continues as necessary). The MC68030 caches assume the higher order address lines (A4-
A31) remain unchanged as the long-word accesses wrap back around to A3/A2=00.
7.4 CPU SPACE CYCLES
FC0–FC2 select user and supervisor program and data areas as listed in Table 4-1. The
area selected by FC0–FC2=$7 is classified as the CPU space. The interrupt acknowledge,
breakpoint acknowledge, and coprocessor communication cycles described in the following
sections utilize CPU space.
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MC68030 USER’S MANUAL
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