MC68030 Datasheet, PDF (430/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Coprocessor Interface Description
10.5.2.5 TRACE EXCEPTIONS. The MC68030 supports two modes of instruction tracing,
discussed in 8.1.7 Trace Exception. In the trace on instruction execution mode, the
MC68030 takes a trace exception after completing each instruction. In the trace on change
of flow mode, the MC68030 takes a trace exception after each instruction that alters the
status register or places an address other than the address of the next instruction in program
counter.
The protocol used to execute coprocessor cpSAVE, cpRESTORE, or conditional category
instructions does not change when a trace exception is pending in the main processor. The
main processor performs a pending trace on instruction execution exception after
completing the execution of that instruction. If the main processor is in the trace on change
of flow mode and an instruction places an address other than that of the next instruction in
the program counter, the processor takes a trace exception after it executes the instruction.
If a trace exception is not pending during a general category instruction, the main processor
terminates communication with the coprocessor after reading any primitive with CA=0.
Thus, the coprocessor can complete a cpGEN instruction concurrently with the execution of
instructions by the main processor. When a trace exception is pending, however, the main
processor must ensure that all processing associated with a cpGEN instruction has been
completed before it takes the trace exception. In this case, the main processor continues to
read the response CIR and to service the primitives until it receives either a null, CA=0,
PF=1 primitive, or until exception processing caused by a take post-instruction exception
primitive has completed. The coprocessor should return the null, CA=0 primitive with PF=0,
while it is completing the execution of the cpGEN instruction. The main processor may
service pending interrupts between reads of the response CIR if IA=1 in these primitives
(refer to Table 10-3). This protocol ensures that a trace exception is not taken until all
processing associated with a cpGEN instruction has completed.
If T1:T0=01 in the MC68030 status register (trace on change of flow) when a general
category instruction is initiated, a trace exception is taken for the instruction only when the
coprocessor issues a transfer status register and scanPC primitive with DR=1 during the
execution of that instruction. In this case, it is possible that the coprocessor is still executing
the cpGEN instruction concurrently when the main processor begins execution of the trace
exception handler. A cpSAVE instruction executed during the trace on change of flow
exception handler could thus suspend the execution of a concurrently operating cpGEN
instruction.
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MC68030 USER’S MANUAL
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