MC68030 Datasheet, PDF (395/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Coprocessor Interface Description
10.4.2 Coprocessor Response Primitive General Format
The M68000 coprocessor response primitives are encoded in a 16-bit word that is
transferred to the main processor through the response CIR. Figure 10-22 shows the format
of the coprocessor response primitives.
15
14 13 12
CA
PC DR
FUNCTION
8
7
0
PARAMETER
Figure 10-22. Coprocessor Response Primitive Format
The encoding of bits [0-12] of a coprocessor response primitive depends on the individual
primitive. Bits [13-15], however, specify optional additional operations that apply to most of
the primitives defined for the M68000 coprocessor interface.
Bit [15], the CA bit, specifies the “come again'” operation of the main processor. When the
main processor reads a response primitive from the response CIR with the come again bit
set to one, it performs the service indicated by the primitive and then reads the response
CIR again. Using the CA bit, a coprocessor can transfer several response primitives to the
main processor during the execution of a single coprocessor instruction.
Bit [4], the PC bit, specifies the pass program counter operation. When the main processor
reads a primitive with the PC bit set from the response CIR, the main processor immediately
passes the current value in its program counter to the instruction address CIR as the first
operation in servicing the primitive request. The value in the program counter is the address
of the F-line operation word of the coprocessor instruction currently executing. The PC bit is
implemented in all of the coprocessor response primitives currently defined for the M68000
coprocessor interface.
When an undefined primitive or a primitive that requests an illegal operation is passed to the
main processor, the main processor initiates exception processing for either an F-line
emulator or a protocol violation exception (refer to 10.5.2 Main-Processor-Detected
Exceptions). If the PC bit is set in one of these response primitives, however, the main
processor passes the program counter to the instruction address CIR before it initiates
exception processing.
When the main processor initiates a cpGEN instruction that can be executed concurrently
with main processor instructions, the PC bit is usually set in the first primitive returned by the
coprocessor. Since the main processor proceeds with instruction stream execution once the
coprocessor releases it, the coprocessor must record the instruction address to support any
possible exception processing related to the instruction. Exception processing related to
concurrent coprocessor instruction execution is discussed in 10.5.1 Coprocessor-
Detected Exceptions.
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MC68030 USER’S MANUAL
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