MC68030 Datasheet, PDF (412/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Coprocessor Interface Description
10.4.15 Transfer Multiple Main Processor Registers Primitive
The transfer multiple main processor registers primitive transfers long-word operands
between one or more of its data or address registers and the coprocessor. This primitive
applies to general and conditional category instructions. Figure 10-35 shows the format of
the transfer multiple main processor registers primitive.
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0
CA PC DR 0
0
1
1
0
0
0
0
0
0
0
0
0
Figure 10-35. Transfer Multiple Main Processor Registers Primitive Format
This primitive uses the CA, PC, and DR bits as previously described. If the coprocessor
issues this primitive with CA=0 during a conditional category instruction, the main processor
initiates protocol violation exception processing.
When the main processor receives this primitive, it reads a 16-bit register select mask from
the register select CIR. The format of the register select mask is shown in Figure 10-36. A
register is transferred if the bit corresponding to the register in the register select mask is set
to one. The selected registers are transferred in the order D0–D7 and then A0–A7.
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A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
Figure 10-36. Register Select Mask Format
If DR=0, the main processor writes the contents of each register indicated in the register
select mask to the operand CIR using a sequence of long-word transfers. If DR=1, the main
processor reads a long-word operand from the operand CIR into each register indicated in
the register select mask. The registers are transferred in the same order, regardless of the
direction of transfer indicated by the DR bit.
10.4.16 Transfer Multiple Coprocessor Registers Primitive
The transfer multiple coprocessor registers primitive transfers from 0-16 operands between
the effective address specified in the coprocessor instruction and the coprocessor. This
primitive applies to general category instructions. If the coprocessor issues this primitive
during the execution of a conditional category instruction, the main processor initiates
protocol violation exception processing. Figure 10-37 shows the format of the transfer
multiple coprocessor registers primitive.
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