MC68030 Datasheet, PDF (278/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Exception Processing
Table 8-5. Exception Priority Groups
Group/Priority
0
1
2
3
4
Exception and Relative Priority
Characteristics
0.0 — Reset
Aborts all processing (instruction or
exception) and does not save old context.
1.0 — Address Error
Suspends processing (instruction or
1.1 — Bus Error
exception) and saves internal context.
2.0 — BKPT #n, CHK, CHK2, cp Mid-Instruction, cp Exception processing is part of instruction
Protocol Violation, cpTRAPcc, Divide by Zero, execution.
RTE, TRAP #n, TRAPV, MMU Configuration
3.0 — Illegal Instruction, Line A, Unimplemented Line Exception processing begins before
F, Privilege Violation, cp Pre-Instruction
instruction is executed.
4.0 — cp Post-Instruction
Exception processing begins when current
4.1 — Trace
4.2 — Interrupt
instruction or previous exception processing
is completed.
0.0 is the highest priority, 4.2 is the lowest.
The priority scheme is very important in determining the order in which exception handlers
execute when several exceptions occur at the same time. As a general rule, the lower the
priority of an exception, the sooner the handler routine for that exception executes. For
example, if simultaneous trap, trace, and interrupt exceptions are pending, the exception
processing for the trap occurs first, followed immediately by exception processing for the
trace and then for the interrupt. When the processor resumes normal instruction execution,
it is in the interrupt handler, which returns to the trace handler, which returns to the trap
exception handler. This rule does not apply to the reset exception; its handler is executed
first even though it has the highest priority because the reset operation clears all other
exceptions.
8.1.13 Return from Exception
After the processor has completed exception processing for all pending exceptions, the
processor resumes normal instruction execution at the address in the vector for the last
exception processed. Once the exception handler has completed execution, the processor
must return to the system context prior to the exception (if possible). The RTE instruction
returns from the handler to the previous system context for any exception.
8-24
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